Mastering RISC-V in SystemVerilog: From ISA to Working CPU Course
by Udemy
Learn to build a RISC-V CPU in SystemVerilog. Run real programs and design custom instructions. Hands-on hardware design course for engineers.
Why this course
- Clear, step-by-step build of a full RISC-V CPU from ground up
- Hands-on implementation with real simulation using Modelsim
- Covers both standard ISA and advanced custom instruction extensions
- Practical projects include real algorithms like Fibonacci and Bubble Sort
